1. Field of the Invention
The present invention relates to a signal transmission technology for enabling high-speed signal transmission between a plurality of LSI chips or a plurality of devices or circuit blocks within a single chip, or between a plurality of boards or cabinets and, more particularly, to a clock generator to be used for high bit-rate signal transmission.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has been greatly improved. In particular, dramatic improvements have been made, for example, in the performance of semiconductor memory devices such as SRAMs (Static Random Access Memories) and DRAMs (Dynamic Random Access Memories), and other semiconductor devices such as processors and switching LSIs.
The improvements in the performance of semiconductor memory devices, processors, and the like have reached the point where system performance cannot be improved further unless the speed of signal transmission between components or elements is increased. Specifically, the speed gap between a DRAM and a processor (i.e., between LSIs), for example, has been widening year by year and, in recent years, this speed gap has been becoming a bottleneck impeding performance improvement for a computer as a whole. Furthermore, with increasing integration and increasing size of semiconductor chips, the speed of signal transmission between elements or circuit blocks within a chip is becoming a major factor limiting the performance of the chip. Moreover, the speed of signal transmission between a peripheral device and the processor/chipset is also becoming a factor limiting the overall performance of the system.
Furthermore, the need for an improvement in signal transmission speed is increasing not only for signal transmission between cabinets or boards (printed wiring boards), for example, between a server and a main storage device or between servers connected via a network, but also for signal transmission between chips or between devices or circuit blocks within a single chip because of increasing integration and increasing size of semiconductor chips and decreasing supply voltage levels (decreasing signal amplitude levels), etc. Moreover, the speed of signal transmission between a peripheral device and the processor/chipset also is becoming a major factor limiting the overall system performance. It is also strongly desired to improve the speed of signal transmission in the so-called back plane (also called the back wiring board BWB) where interconnections are made between circuit boards within an apparatus.
Generally, in high-speed signal transmission between circuit blocks or chips or between cabinets, the clock to be used to discriminate between data “0” (low level “L”) and data “1” (high level “H”) is generated (recovered) at the receiving circuit side. To achieve correct signal transmission and reception, it is required that variations in the clock rise time (deviations from the ideal periodic timing), called jitter, be reduced, and it is therefore strongly desired to provide a clock generator that can generate an accurate, low-jitter clock.
The prior art and its associated problem will be described in detail later with reference to relevant drawings.